1. Field of the Invention
This invention relates to a combinational logic circuit intended for reducing power consumption, its design method and integrated circuit device.
2. Description of the Prior Art
Most of the power consumption in CMOS circuit results from charging and discharging of load and is proportional to the square of voltage of an applied power. Therefore, a method of reducing power voltage is very effective for reduction of power consumption. However, because circuit delay time is increased if the power voltage is reduced, if the power voltage of each gate is reduced without any special reason, like for example, reducing the power voltages of all gates, the timing restriction (maximum delay time) requested for a circuit is not satisfied so that reduction of performance is induced.
Japanese Patent Application Laid-Open Publication No. 7-249067 has disclosed an art for achieving reduction of consumption power without increasing the maximum signal transmission delay time of critical path.
FIG. 1 is a block diagram showing an example of a conventional semiconductor integrated circuit (first prior art example) disclosed in the above Japanese application.
In this semiconductor integrated circuit, a plurality of registers 101, 102, 103, 104 comprising flip-flop circuits operating according to clock CLK and combinational circuits 111, 112, 113, 114 are disposed alternately with these registers 101-104, the registers and combinational circuits being connected in series between INPUT and OUTPUT.
The combinational circuit 113 having the critical path is driven by a high power supply (3v) and other combinational circuits 111, 112, 114 having no critical path are driven by a low power supply (2v). An output portion of the register 102 located ahead of the combinational circuit 113 having the critical path is provided with a level converter for converting a low-voltage signal to a high-voltage signal.
However, according to the aforementioned method, timing analysis is conducted between the registers. Then, a circuit 113 (having no sufficient allowance in timing) having a critical path is operated with a high voltage power supply (3v) and other combinational circuits 111, 112, 114 (having an allowance in timing) having no critical path are operated by a low voltage power supply (2v).
In this method in which each register is sectioned for carrying out timing analysis so as to attain reduction of power consumption, detailed timing analysis in each signal path inside the combinational circuit is not carried out. Thus, this prior art has a limitation in reduction of power consumption therein.
That is, a number of signal paths exist in each of the combinational circuits provided between the registers and the combinational circuit 113 set by a high voltage power supply as its operating power contains a number of signal paths as well as critical path. The number of signal paths except this critical path are paths having a sufficient allowance in timing. Although the operating voltage can be reduced for the gates on this path, the aforementioned prior art patent did not pay attention to this point.
FIG. 2 is a circuit diagram showing an example of the combinational circuit in a semiconductor integrated circuit.
In this combinational circuit, gates 151, 152, 153, 154 are connected between a primary input terminal i1 and a primary output terminal o1, and gates 155, 156 are connected between a primary input terminal i2 and a primary output terminal o2. Further, gates 157, 158, 159 are connected between a primary input terminal i3 and a primary output terminal o3 and a gate 160 is connected between a primary input terminal i4 and a primary output terminal o4. Further, a primary input terminal i5 is connected to a gate 159.
When, in the logic circuit having such a structure, gates to which high operating voltage VDDH is supplied and gates to which low operating voltage VDDL is supplied are determined while the timing restriction is satisfied, a structure as shown in FIG. 3 is sometimes generated in the prior art. In FIG. 3, between the VDDL gate distinguished by hatching and VDDH gate are level converters 171-176. That is, the structure shown in FIG. 3 has a number of connection structures in which the output of the VDDL gate is included in the input of the VDDH gate. Thus, a number of level converters for amplifying an amplitude of output voltage of the VDDL gate up to a magnitude necessary for driving the VDDH gate are required.
FIG. 4 shows a typical level converter circuit. This level converter circuit comprises a pair of P-channel transistors MP2, MP3 one drain of which is connected to the other gate thereof. The P-channel transistor MP2 is connected to the ground level by means of the N-channel transistor MN2 and the other P-channel transistor MP3 is connected to the ground level by means of the second N-channel transistor MN3. These N-channel transistors MN2, MN3 are operated by the operating voltage VDDL and are turned ON/OFF by inputting the output signal of a gate (not shown) operated by the operating voltage VDDL. Because the inverter IB1 is provided between the MN2 and MN3, when one of them is turned ON, the other is turned OFF.
Even if a circuit operated by the operating voltage VDDL is directly connected to the output of a circuit operated by the operating voltage VDDH, the high level of the input of the circuit operated by the operating voltage VDDL is raised up to the operating voltage VDDH. Thus, the P-channel transistor is completely turned off so that no DC current flows.
The level converter having the aforementioned structure has a function for interrupting DC current, however consumes a considerably large dynamic power at the time of switching. Therefore, as the number of the level converters increases, the amount of power consumed in the entire level converters increases, thereby weakening the effect of reduction of power consumption. Because the installation of the level converter consumes a considerably large dynamic power, a structure in which a number of the level converters are inserted does not coincide with a purpose for reducing the power consumption.
To solve this problem, this applicant has already proposed the following method (second prior art example) (Japanese Patent Application Laid-Open Publication No. 9-162720).
According to this method, as shown in FIG. 5, the VDDH gates are gathered on the input terminal side of the combinational logic circuit so as to form a VDDH cluster 180 and the VDDL gates are gathered on the output terminal side so as to form a VDDL cluster 181. According to this method, only by inserting the level converters 191-194 just before partial output terminals, the power voltage of many gates can be reduced to VDDL level so that the power consumption can be largely reduced.
According to this circuit design method, first of all, a logic circuit in which the timing restriction is satisfied when the operating voltage VDDH is supplied to the entire gate of the combinational circuit is designed and subsequently, whether or not the operating voltage VDDH can be changed to the operating voltage VDDL is considered about each of the gates one by one from the primary output terminal to the primary input terminal. On this consideration stage, if the entire logic circuit satisfies the timing restriction when the operating voltage VDDL is supplied to one gate, the voltage to be supplied to that gate is determined to be the operating voltage VDDL. If the timing restriction is not satisfied, the voltage to be supplied to that gate and a gate connected to its input terminal is determined to be the operating voltage VDDH.
However, the above described second prior art example has the following problem.
This example will be described concretely with reference to FIGS. 6A, 6B.
A logic circuit in which a predetermined timing restriction is satisfied when the operating voltage VDDH is supplied to the entire gate of the combinational circuit is designed. This logic circuit is as shown in FIG. 6A to simplify the description thereof. That is, between a primary input terminal I1 and a primary output terminal O1 are connected gates 201, 202, 203, 204. Between a primary input terminal I2 and a primary output terminal O2 are connected gates 211, 212, 213. On the other hand, an output of the gate 202 is connected to the other input terminal of the gate 213.
According to the aforementioned design method, in such a logic circuit, a gate for supplying the operating voltage VDDH and a gate for supplying the operating voltage VDDL while the timing restriction is satisfied are determined. The logic circuit shown in FIG. 6A contains three signal paths. A first path P1 is a path extending from the input terminal I1 to the output terminal O1 (input terminal I1.fwdarw.gates 201.fwdarw.gate 202.fwdarw.gate 203 gate 204.fwdarw.output terminal O1). A second path P2 is a path extending from the input terminal I1 to the output terminal O2 (input terminal I1.fwdarw.gate 201 .fwdarw.gate 202.fwdarw.gate 213.fwdarw.output terminal O2). A third path P3 is a path extending from the input terminal I2 to the output terminal O2 (input terminal I2.fwdarw.gate 211.fwdarw.gate 212.fwdarw.gate 213.fwdarw.output terminal O2).
About each of these three paths P1, P2, P3, whether or not the operating voltage VDDH can be changed to the operating voltage VDDL is considered with respect to each of the gates one by one from the primary output terminal to the primary input terminal. As a result, a logic circuit having a structure shown in FIG. 6B is realized.
That is, only the gates 203, 204 are the VDDL gates, and assuming that the output terminal O1 is the VDDH level, the level converter 214 is inserted between the gate 204 and the output terminal O1.
At this time, the VDDL gate output cannot be connected to the input of the VDDH gate. Thus, when the power voltage of a predetermined gate (gate 213) cannot be lowered to the VDDL level because of the timing restriction of a path (second path P2), the gates 211, 212 on the input side with respect to the gate 213, located on another path (third path P3) passing the gate 213 cannot be converted to the VDDL gate even if there is an allowance in timing.
As described above, the second prior art example has a point to be improved in viewpoints of reduction of the power consumption.